In order to improve the density of the memory device, the industry has worked extensively at developing a method for reducing the size of a two-dimensional arrangement of memory cells. As the size of the memory cells of the two-dimensional (2D) memory devices continues to shrink, signal conflict and interference will significantly increase, so that it is difficult to perform operation of multi-level cell (MLC). In order to overcome the limitations of 2D memory device, the industry has developed a memory device having a three-dimensional (3D) structure to improve the integration density by three-dimensionally arrange the memory cell d on the substrate.
Specifically, a multilayer laminated structure (e.g., a plurality of ONO structures of alternating oxide and nitride) may firstly deposited on the substrate; by an anisotropic etching process for etching the multilayer laminated structure on the substrate, a plurality of channel through-holes distributed along the word line (WL) of memory cell extending direction and perpendicular to the substrate surface are formed (may extend through to the substrate surface or with a certain over-etch); a plurality of pillar-shaped channels are formed in the channel through-holes by depositing polycrystalline silicon material; the multilayer laminated structure is etched along the WL direction to form a plurality of trenches through to the substrate, exposing the multilayer stack surrounding the pillar-shaped channels; a certain type of materials in the stack is removed by wet etching (e.g., using hot phosphoric acid to remove nitrogen silicon, or HF to remove silicon oxide), leaving a plurality of projecting structures laterally distributed around the pillar-shaped channels; a gate dielectric layer (such as high-k dielectric materials) and a gate conductive layer (e.g., Ti, W, Cu, Mo, etc.) are deposited on the side walls of the projecting structures in the trenches to form a gate stack; a portion of the gate stack out of the lateral plane of the projecting structures is removed by vertical anisotropic etching until the gate dielectric layer on the side of the projecting structures is exposed; the laminated structure is etched to form a plurality of source/drain contacts, and rear end of the manufacturing processes are completed. Here, a portion of projecting structures of the laminated structure leaving on the sidewall of pillar-shaped channels forms a plurality of spacers between the gate electrodes, leaving the gate stacks sandwiched between the spacers as control electrodes. When a voltage is applied to the gates, the fringe field of the gate will enable a plurality of source and drain regions to be formed on sidewalls of pillar-shaped channels made of e.g. polycrystalline silicon material, thereby constituting a gate array composed of a plurality of MOSFETs series-parallel coupled to record the stored logic states.
In above device structure, the control gate and the gate dielectric layer (typically a silicon nitride based dielectric, with simple process and good bottom contact characteristics) surround polycrystalline silicon channel layer which is usually hollow pillar-shape (with better control for sub-threshold characteristic control), the inner side of the pillar-shaped channel layer may be further filled with dielectric layer (e.g., silicon oxide, in order to facilitate integration). However, studies show that the growth temperature of oxide in the gate-last process can greatly affect the thinning of native oxide and its surface roughness (an extremely thin silicon oxide layer formed due to local heating and other factors during the formation of the polycrystalline silicon channel layer) at the interface between the polycrystalline silicon channel layer, the gate dielectric layer and the filled dielectric layer, furthermore the interface state defects caused by the surface roughness, as well as a large number of gaps and gap interface states between the crystalline grains inside the polycrystalline silicon channel layer make the channel carrier mobility of the device decreased, thereby reduce the memory cell reliability.